ESD Quizes

1. How many external interrupt lines does the ARM7TDMI have? Ans: 2

2. Which of the following is illegal? Options: a) ADD R8,R9,#0x1F b) ADD R1,R1,R2 c) ADD R5,R16,R3 d) None of the mentioned. Ans: ADD R5,R16,R3

3. After the execution of LDR R0, [R1], #4 , what will be the value of R0 and R1? Ans: R0 = mem[R1] , R1= R1+4

4. Indicate whether the instruction STR r6, [r4, #4] use ___________________ addressing modes. Options: a) pre-indexed, b) immediate, c) post-indexed, d) None of the mentioned Ans: pre-indexed

5. In the ARM Nomenclature ARMxTDMI, D and M stand for ? Ans: Debug and Multiplier

6. Which ARM7TDMI processor mode is unprivileged mode? Options: a) FIQ, b) IRQ, c) System, d) User Ans: User

7. What mode does the processor have to be in to move the contents of the SPSR to the CPSR? Ans: Any privileged mode

8. What is the order of the ARM7TDMI processor to execute the instruction? Ans: Fetch - Decode - Execute

9. What is micro-controller? Ans: It is a microprocessor along with memory and I/O interfaces on the same chip.

10. ARM7TDMI has ___________________ operating states. Ans: ARM and THUMB

11. If an ARM7TDMI processor encounters an undefined instruction, from what address will it begin fetching instructions after it changes to Undefined mode? Ans: 0x00000004

12. What will be the value of R2 after the execution of the "LDR R1, [R2 LSL R3]!"  instruction if R2 = 0x00200000, R3 = 0x02. Ans: 0x00800000

13. The locality of reference property justifies the use of  ___________________. Ans: cache memory

14. Calculate the effective address of the "STRH r9, [r3, r4]" instruction, if register r3 = 0x4000 and register r4 = 0x20. Ans: 0x4020

15. Which of the following statement is false? Select one:

    • DRAM is faster as compared to SRAM

    • SRAM is faster as compared to DRAM

    • DRAM requires less power than SRAM

    • All of the mentioned

Ans: DRAM is faster as compared to SRAM

16. Which of the following statements is/are false? Select one:

    • In Von Neumann architecture, external busses for program memory and data memory

    • In Von Neumann architecture, shared bus between the program memory and data memory

    • In Hardvard architecture, shared bus between the program memory and data memory

    • In Hardvard architecture, separate busses for program memory and data memory

Ans: In Hardvard architecture, shared bus between the program memory and data memory

17. Which of the following statements is/are false with regards to cache? Select one:

    • cache is smaller in size than the main memory

    • cache is slower than main memory

    • cache increases the performance of a memory system

    • all of the mentioned

Ans: cache is slower than main memory

18. The increment after (IA) instruction is equivalent to which of the following stack operations. Select one: a) Empty Descending, b)Fully Ascending, c) Fully Descending, d) Empty Ascending. Ans: Empty Ascending

19. A general-purpose microprocessor normally needs which of the following devices to be attached to it? Select one: a) RAM, b) ROM, c) I/O, d) All of the mentioned. Ans: All of the mentioned

20. What does "Embedded systems may simultaneously control some operations that run at slow rates and others that run at high rates" imply? Options: a) Real-time, b) Multi-rate, c) Single functioned, d) Reactive. Ans: Multi-rate

21. The function of link register in ARM7TDMI is  ___________________. Ans: To store return address whenever subroutine is called

22. Which of the following statement is correct in regards to memory? Select one:

    • The faster, smaller memory are always closer to the processor

    • The memory that is farthest away from the processor is the costliest

    • As we move away from the processor, speed increases

    • None of the mentioned

Ans: The faster, smaller memory are always closer to the processor

23. What is another way of writing the "MOV PC, LR"  line of code? Ans: MOV r15, r14

24. On an ARM7TDMI, in any given mode, how many registers does a programmer see at one time? Ans: 17 for User mode, 18 for remaining modes

25. If the current value of R13 is 0x80C; if the stack is ED then after we store a 32 bit data, the new value of R13 will be? Ans: 0x808

1. Which register is used to switch between privileged and unprivileged Thread modes in the ARM Cortex-M4 processor? Ans: CONTROL

2. What is the purpose of the stack pointer register in ARM Cortex M4 processor? Select one:

   • To store the address of the top of the stack

   • To store the address of the next instruction to be executed

   • To store the current value of the program counter

   • To store the base address of the stack

Ans: To store the address of the top of the stack

3. Which of the following is not an exception type in ARM Cortex M4? Options: a) Reset, b) DMA, c) HardFault, d) NMI. Ans: DMA

4. Which of the following is a feature of the APB protocol in the AMBA bus architecture? Select one:

   • It is designed for high bandwidth peripherals

   • It supports burst transfers

   • It is used for connecting low bandwidth peripherals

   • All of the mentioned.

Ans: It is used for connecting low bandwidth peripherals

5. What happens after reset and before the Cortex-M processor starts executing the program? Ans: The processor reads the first two words from the memory

6. Which of the following is not a system control register in the ARM Cortex-M4 processor? Select one:

   • Stack Pointer Register (SP)

   • Fault Mask Register (FAULTMASK)

   • Priority Mask Register (PRIMASK)

   • Base Priority Register (BASEPRI)

Ans: Stack Pointer Register (SP)

7. What is the highest priority exception in ARM Cortex M4 processor? Options: a) PendSV, b) BusFault, c) NMI, d) SVCall. Ans: NMI

8. What is the final step in the Cortex-M4 processor reset sequence? Select one:

   • Enabling interrupts through the NVIC

   • Initializing the stack pointer

   • Fetching instructions from the reset vector

   • None of the mentioned

Ans: Fetching instructions from the reset vector

9. Which register is used to store the status flags in the ARM Cortex-M4 processor? Ans: APSR

10. What is the purpose of the Hard Fault exception in ARM Cortex M4? Ans: To handle unrecoverable system failures

11. Why do we need a sample-and-hold circuit before an analog-to-digital converter for sampling an analog signal? Select one:

    • To ensure that A/D converter output stabilizes faster.

    • To ensure that the sampling rate of the signal can be reduced.

    • To ensure that the input to A/D converter do not change during conversion

    • None of the mentioned.

Ans: To ensure that the input to A/D converter do not change during conversion

12. During and just after reset, STM32F407 I/O ports are configured in  ___________________ mode. Ans: Input floating

13. What is the resolution of the ADC in STM32F407 micro-controller? Ans: 12bits

14. Which of the following is not a feature of the ARM Cortex-M4 processor's NVIC (Nested Vectored Interrupt Controller)? Select one:

    • Fully access the NVIC from privileged mode

    • Prioritization of interrupts

    • Supports up to 240 external interrupts

    • Fully access the NVIC from unprivileged mode

Ans: Fully access the NVIC from unprivileged mode

15. Which operating mode of ARM Cortex M4 processor is entered when an exception occurs? Ans: Handler mode

16. Which register is used to store the address of the next instruction to be executed in the ARM Cortex-M4 processor? Ans: PC

17. Which register is used to disable all interrupts in the ARM Cortex-M4 processor? Ans: PRIMASK

18. Which exception is used for scheduling tasks in RTOS? Ans: PendSV

19. Which of the following is not a feature of the ARM Cortex-M4 processor? Select one:

    • NVIC closely integrated

    • Multiple high-performance bus interfaces

    • Thumb-2 instruction set support

    • Integrated floating-point unit

Ans: Integrated floating-point unit

20. Which of the following is/are feature/s of the AHB-lite protocol? Select one:

    • burst transfers

    • single-clock edge operation

    • wide data bus configurations

    • All of the mentioned

Ans: All of the mentioned